1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing an LCD device.
2. Discussion of the Related Art
In general, an LCD device includes an LCD panel to display images and an external driving circuit to supply driving signals to the LCD panel. In addition, the LCD panel includes first and second transparent substrates (glass substrates) bonded to each other having a predetermined interval therebetween, and a liquid crystal material injected between the first and second substrates. The first substrate includes a plurality of gate and data lines crossing each other to define pixel regions, a plurality of pixel electrodes in the respective pixel regions, and a plurality of thin film transistors at respective crossing portions of the gate and data lines to supply video signals transmitted along the data lines to the respective pixel electrodes according to gate signals transmitted along the gate lines. The second substrate includes a black matrix layer that excludes transmission of light from portions of the first substrate except within the pixel regions, a red (R)/green (G)/blue (B) color filter layer for producing colored light corresponding to the respective pixel regions, and a common electrode for driving liquid crystal molecules of the liquid crystal material with the pixel electrode of the first substrate. Accordingly, as turn-ON signals are sequentially supplied to the gate lines, the data signals are supplied to the pixel electrode of the corresponding line, thereby displaying images.
In the LCD device, an active layer of the thin film transistor is formed of dehydrogenated amorphous silicon (a-Si), since the dehydrogenated a-Si may be used for fabricating the glass substrate during low-temperature processes. However, since the dehydrogenated a-Si has both weak Si—Si bonds and dangling bond due to its disordered atomic arrangement, use of the dehydrogenated a-Si may cause instability when driving the LCD device during light irradiation and induction of an electric field to the liquid crystal material. Specifically, since the a-Si has a low field effect mobility of 0.1 cm2/Vs to 1.0 cm2/Vs and decreased reliability, the a-Si is not appropriate for driving circuitry of an LCD device. Accordingly, the driving circuit is formed on an additional printed circuit board (PCB) substrate instead of the first substrate, wherein the first substrate and the PCB substrate are connected with each other by using a tape carrier package (TCP) and an integrated circuit (IC), thereby increasing manufacturing costs of the LCD device. In addition, as resolution of the LCD panel of the LCD device increases, external pad pitch increases. Thus, it is difficult to perform the TCP bonding process due for connecting the gate and data lines to the TCP.
However, polysilicon has a field effect mobility higher than that of the amorphous silicon a-Si, and is commonly used for the driving circuitry of the LCD device. Accordingly, it is possible to both simplify manufacturing process and decrease manufacturing costs. Since the polysilicon thin film transistor (TFT) has greater electron/hole mobilities than the a-Si TFT, the polysilicon TFT may be configured as a complementary metal-oxide semiconductor (CMOS) TFT. Thus, instead of bonding the driving circuit IC onto a separate substrate, polysilicon structures used for the driving circuitry are formed on the substrate such that the driving circuitry is formed simultaneously with the TFT of a pixel part. Currently, it is possible to form the polysilicon TFT at temperatures similar to that of the a-Si TFT using laser crystallization methods.
FIG. 1 is a block diagram of a polysilicon LCD device according to the related art. In FIG. 1, a polysilicon LCD device includes a pixel part 4 and a driving circuit part 3 formed on a second substrate 2. The pixel part 4 includes a plurality of gate lines 6 arranged on the second substrate 2 along a first direction and a plurality of data lines 6 arranged along a second direction perpendicular to the first direction, thereby forming a plurality of pixel region in a matrix-type configuration. The driving circuit part 3 is formed on the second substrate 2 to provide driving and data signals to the pixel part 4. Accordingly, a pixel electrode 1 and a TFT T are formed within the pixel region at a crossing portion of the gate and data lines 6 and 8. Thus, gate and data drivers 3a and 3b of the driving circuit part 3 provide control and data signals to the pixel electrode 1 of the pixel region through the gate and data lines 6 and 8. When turn-ON signals are sequentially supplied to the gate line 6, the data signals are supplied to the pixel electrode 1 of the corresponding gate line, thereby displaying images. The gate and data drivers 3a and 3b are connected using an external signal input terminal 5, wherein the gate and data drivers 3a and 3b control external signals input through the external signal input terminal 5, and output the controlled external signals to the pixel electrode 1. In addition, the gate and data drivers 3a and 3b make use of CMOS TFTs (not shown) as an inverter for outputting the signals.
FIGS. 2A to 2H are cross sectional views of manufacturing process steps of an LCD device according to the related art. In FIG. 2A, a polysilicon layer is deposited along an entire surface of a substrate 100 having a pixel part and a driving circuit part. Then, the polysilicon layer is selectively patterned by photolithographic processes, thereby forming first, second, and third semiconductor layers 10a, 10b, and 10c at the pixel part and the driving circuit part (the first mask).
In FIG. 2B, impurity ions are implanted into a predetermined portion of the semiconductor layer 10a at the pixel part, thereby forming a first storage capacitor electrode 17a. When the first semiconductor layer 10a of the pixel part is formed of n-type material, a first photoresist 61 is deposited along an entire surface of the substrate 100, and only a portion corresponding to the first storage capacitor electrode 17 is exposed by photolithographic processes. Then, n-type impurity ions are selectively implanted into a portion of the first storage capacitor electrode 17a, thereby forming a conductive portion (the second mask).
In FIG. 2C, after removing the first photoresist 61, a heat treatment or a laser irradiation is performed thereto to activate the n-type impurity ions. Then, an insulating material, such as silicon oxide or silicon nitride, is coated along an entire surface of the substrate 100, thereby forming a gate insulating layer 30. Next, a metal layer (not shown) of Al, Al alloy, or Cr is coated along an entire surface of the substrate 100 including the gate insulating layer 30 (in FIG. 2B). Then, the metal layer (not shown) is selectively patterned by photolithographic processes, thereby forming first, second, and third gate electrodes 20a, 20b, and 20c on the gate insulating layer 30 corresponding to the first, second, and third semiconductor layers 10a, 10b, and 10c. In addition, a second storage capacitor electrode 17b is formed on the first storage capacitor electrode 17a (the third mask). When patterning the metal layers, the metal layer for each of the first, second, and third gate electrodes 20a, 20b, and 20c is patterned to be positioned in middle portion of each of the first, second, and third semiconductor layers 10a, 10b, and 10c. In addition, the metal layer for the second storage capacitor electrode 17b is formed to completely cover the first storage capacitor electrode 17.
In FIG. 2D, lightly doped n-type impurity ions are implanted into an entire surface of the substrate 100 by using the first, second, and third gate electrodes 20a, 20b, and 20c and the second storage capacitor electrode 17b as a mask, thereby forming LDD regions 21a, 21b, 22a, 22b, 23a, and 23b in the first, second, and third semiconductor layers 10a, 10b and 10c. In addition, channel regions 21c, 22c, and 23c are formed in the first, second, and third semiconductor layers 10a, 10b, and 10c corresponding to the gate electrodes 20a, 20b, and 20c, respectively.
In FIG. 2E, a second photoresist 62 is deposited along an entire surface of the substrate 100 including the LDD regions 21a, 21b, 22a, 22b, 23a, and 23b. Then, the second photoresist 62 is patterned by photolithographic processes to remain as a shape for covering the LDD regions 21a and 21b of the first semiconductor layer 10a corresponding to both sides of the first gate electrode 20a and the third semiconductor layer 10c. Next, heavily doped n-type impurity ions are implanted into the first and second semiconductor layers 10a and 10b by using the patterned second photoresist 62 as a mask, whereby first source/drain regions 31a/31b are formed in the exposed portions of the first semiconductor layer 10a, and nMOS-type second source/drain regions 32a/32b are formed in the exposed portions of the second semiconductor layer 10b (the fourth mask).
In FIG. 2F, after removing the second photolithography 62, a third photoresist 63 is deposited, and then patterned to cover an entire surface of the substrate 100, except for the third semiconductor layer 10c, by photolithographic processes. Then, heavily doped p-type impurity ions are implanted into the third semiconductor layer 10c by using the patterned third photoresist 63 as a mask, thereby forming pMOS-type third source/drain regions 33a/33b (the fifth mask).
The aforementioned doping method is commonly referred to as counter doping. When implanting the lightly doped n-type impurity ions, an ionization concentration of the impurity ions for the third semiconductor layer 10c is about 1014/cm3. In addition, when implanting the heavily doped p-type impurity ions, an ionization concentration of the impurity ions for the third semiconductor layer 10c is about 1018/cm3. By implanting the heavily doped p-type impurity ions, the region of the lightly doped n-type impurity ions is changed to the region of the heavily doped p-type impurity ions.
After completing the impurity ion implanting process, the pixel part has the first semiconductor layer 10a including the first source/drain regions 31a/31b to which the heavily doped n-type impurity ions are implanted, and the LDD region 31d to which the lightly doped n-type impurity ions are implanted, and the channel region 23c. In addition, the driving part has the second semiconductor layer 10b and the third semiconductor layer 10c. Accordingly, the second semiconductor layer 10b includes the second source and drain regions 32a and 32b to which the heavily doped n-type impurity ions are implanted, and the channel region 22c. Similarly, the third semiconductor layer 10c includes the third source and drain regions 33a and 33b to which the heavily doped p-type impurity ions are implanted, and the channel region 23c. 
In FIG. 2G, the third photoresist 63 is removed, and then an insulating interlayer 200 is formed by depositing an insulating layer, such as silicon nitride, along an entire surface of the substrate 100. Then, the insulating interlayer 200 is selectively patterned by photolithographic processes, thereby forming a first contact hole for exposing the first source region 31a of the first semiconductor layer 10a, the second source and drain regions 32a and 32b of the second semiconductor layer 10b, and the third source/drain regions 33a and 33b of the third semiconductor layer 10c (the sixth mask). Next, a metal material, such as Al, is deposited along an entire surface of the substrate 100, and then selectively patterned by photolithographic processes, thereby forming a data line (not shown) of the first semiconductor layer 10a, a first source electrode 40 projecting from the data line, second source and drain electrodes 25 and 26 of the second semiconductor layer 10b, and third source and drain electrodes 26 and 27 of the third semiconductor layer 10c. In addition, the second drain region 32b is electrically connected with the third source region 33a. 
In FIG. 2H, a passivation layer 300 is formed by depositing an insulating material along an entire surface of the substrate 100. Then, the gate insulating layer 30, the insulating layer 200, and the passivation layer 300 corresponding to the first drain region 31b of the first semiconductor layer 10a are selectively removed by photolithographic processes, thereby forming a second contact hole for exposing the first drain region 31b of the first semiconductor layer 10a (the eighth mask). Next, an indium-tin-oxide (ITO) layer is deposited along an entire surface of the substrate 100 including the second contact hole, and then selectively patterned by photolithographic processes, thereby forming a pixel electrode 50 (the ninth mask). Accordingly, in the pixel part, the n-type TFT including the first semiconductor layer 10a doped as the n-type and the first gate electrode 20a is formed. In addition, in the driving circuit part, the CMOS TFT is formed, wherein the CMOS TFT includes the n-type TFT having the second semiconductor layer 10b doped as the n-type and the second gate electrode 20b, and the p-type TFT having the third semiconductor layer 10c doped as the p-type and the third gate electrode 20c. 
However, the method of manufacturing the LCD device according to the related art has the following disadvantages. During the process of forming the storage capacitor, an additional mask is required for implanting the impurity ions into the first storage capacitor electrode. In addition, when patterning the n-type TFT and the p-type TFT of the driving circuit part, two masks are required for implanting the n-type and p-type impurity ions into the respective semiconductor layers for the TFT. Accordingly, as the number of masks increases, manufacturing costs increase, thereby lowering productivity and yield.